Menu music and DAS on menu items.
This commit is contained in:
Randy Thiemann
parent
fd40ba2ecc
commit
6d980285e3
BIN
bin/DMGTRIS.GBC
BIN
bin/DMGTRIS.GBC
Binary file not shown.
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@ -37,5 +37,11 @@ SECTION "Bank ID 2", ROMX[$4000], BANK[2]
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ENDR
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ENDR
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db $02
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db $02
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SECTION "Bank ID 3", ROMX[$4000], BANK[3]
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REPT 7
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rst $00
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ENDR
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db $03
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ENDC
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ENDC
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@ -143,6 +143,7 @@ DEF SFX_LEVELLOCK EQU 14
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DEF SFX_LEVELUP EQU 15
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DEF SFX_LEVELUP EQU 15
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DEF SFX_RANKUP EQU 16
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DEF SFX_RANKUP EQU 16
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DEF SFX_READYGO EQU 17
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DEF SFX_READYGO EQU 17
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DEF MUSIC_MENU EQU $EE
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DEF STACK_SIZE EQU 64
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DEF STACK_SIZE EQU 64
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DEF GAME_OVER_R10 EQU 133
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DEF GAME_OVER_R10 EQU 133
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@ -1,30 +0,0 @@
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; DMGTRIS
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; Copyright (C) 2023 - Randy Thiemann <randy.thiemann@gmail.com>
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; This program is free software: you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation, either version 3 of the License, or
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; (at your option) any later version.
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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; You should have received a copy of the GNU General Public License
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; along with this program. If not, see <https://www.gnu.org/licenses/>.
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IF !DEF(BUILD_DATE_ASM)
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DEF BUILD_DATE_ASM EQU 1
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SECTION "Build date", ROM0
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db "Built "
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BuildDate::
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db __ISO_8601_UTC__
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db 0
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ENDC
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
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@ -0,0 +1,241 @@
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# DMGTRIS
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# Copyright (C) 2023 - Randy Thiemann <randy.thiemann@gmail.com>
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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from construct import Struct, Const, Int32ul, Int16ul, Int8ul, Bytes
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vgm_header = Struct(
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"magic" / Const(b"Vgm "),
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"eof_offset" / Int32ul,
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"version" / Int32ul,
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"sn76489_clock" / Int32ul,
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"ym2413_clock" / Int32ul,
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"gd3_offset" / Int32ul,
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"total_samples" / Int32ul,
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"loop_offset" / Int32ul,
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"loop_samples" / Int32ul,
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"rate" / Int32ul,
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"sn_fb" / Int16ul,
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"sn_w" / Int8ul,
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"sn_c" / Int8ul,
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"ym2612_clock" / Int32ul,
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"ym2151_clock" / Int32ul,
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"vgm_data_offset" / Int32ul,
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"seg_pcm_clock" / Int32ul,
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"seg_pcm_intf_reg" / Int32ul,
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"rf5c68_clock" / Int32ul,
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"ym2203_clock" / Int32ul,
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"ym2608_clock" / Int32ul,
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"ym2610_clock" / Int32ul,
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"ym3812_clock" / Int32ul,
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"ym3526_clock" / Int32ul,
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"y8950_clock" / Int32ul,
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"ymf262_clock" / Int32ul,
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"ymf278b_clock" / Int32ul,
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"ymf271_clock" / Int32ul,
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"ymz280b_clock" / Int32ul,
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"rf5c164_clock" / Int32ul,
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"pwm_clock" / Int32ul,
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"ay8910_clock" / Int32ul,
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"ay8910_type" / Int8ul,
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"ay8910_flags" / Int8ul,
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"ym2203_ay8910_flags" / Int8ul,
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"ym2608_ay8910_flags" / Int8ul,
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"volume_mod" / Int8ul,
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"reserved_0" / Bytes(1),
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"loop_base" / Int8ul,
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"loop_modifier" / Int8ul,
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"dmg_clock" / Int32ul,
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"nes_apu_clock" / Int32ul,
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"multi_pcm_clock" / Int32ul,
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"upd7759_clock" / Int32ul,
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"okim6258_clock" / Int32ul,
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"okim6258_flags" / Int8ul,
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"k054539_flags" / Int8ul,
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"c140_chip_type" / Int8ul,
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"reserved_1" / Bytes(1),
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"okim6295_clock" / Int32ul,
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"k051649_k052539_clock" / Int32ul,
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"k054539_clock" / Int32ul,
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"huc6280_clock" / Int32ul,
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"c140_clock" / Int32ul,
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"k053260_clock" / Int32ul,
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"pokey_clock" / Int32ul,
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"qsound_clock" / Int32ul,
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"scsp_clock" / Int32ul,
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"extra_hdr_offset" / Int32ul,
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"wonder_swan_clock" / Int32ul,
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"vsu_clock" / Int32ul,
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"saa1099_clock" / Int32ul,
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"es5503_clock" / Int32ul,
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"es5505_es5506_clock" / Int32ul,
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"es5503_num_channels" / Int8ul,
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"es5505_es5506_num_channels" / Int8ul,
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"c352_clock_div" / Int8ul,
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"reserved_2" / Bytes(1),
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"x1_010_clock" / Int32ul,
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"c352_clock" / Int32ul,
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"ga20_clock" / Int32ul,
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"reserved_3" / Bytes(28)
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)
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b3_command = Struct(
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"command" / Const(b'\xB3'),
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"reg" / Int8ul,
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"data" / Int8ul
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)
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register_names = [
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"REG_UNK", # 0x00
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"REG_UNK", # 0x01
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"REG_UNK", # 0x02
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"REG_UNK", # 0x03
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"REG_UNK", # 0x04
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"REG_UNK", # 0x05
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"REG_UNK", # 0x06
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"REG_UNK", # 0x07
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"REG_UNK", # 0x08
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"REG_UNK", # 0x09
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"REG_UNK", # 0x0A
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"REG_UNK", # 0x0B
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"REG_UNK", # 0x0C
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"REG_UNK", # 0x0D
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"REG_UNK", # 0x0E
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"REG_UNK", # 0x0F
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"REG_NR10_CH1_SWEEP", # 0x10
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"REG_NR11_CH1_LENDT", # 0x11
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"REG_NR12_CH1_VOLEV", # 0x12
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"REG_NR13_CH1_FRQLO", # 0x13
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"REG_NR14_CH1_FRQHI", # 0x14
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"REG_UNK", # 0x15
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"REG_NR21_CH2_LENDT", # 0x16
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"REG_NR22_CH2_VOLEV", # 0x17
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"REG_NR23_CH2_FRQLO", # 0x18
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"REG_NR24_CH2_FRQHI", # 0x19
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"REG_NR30_CH3_DACEN", # 0x1A
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"REG_NR31_CH3_LENGT", # 0x1B
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"REG_NR32_CH3_VOLUM", # 0x1C
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"REG_NR33_CH3_FRQLO", # 0x1D
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"REG_NR34_CH3_FRQHI", # 0x1E
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"REG_UNK", # 0x1F
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"REG_NR41_CH4_LENGT", # 0x20
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"REG_NR42_CH4_VOLEV", # 0x21
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"REG_NR43_CH4_FQRND", # 0x22
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"REG_NR44_CH4_CNTRL", # 0x23
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"REG_NR50_MVOLVINPN", # 0x24
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"REG_NR51_MASTERPAN", # 0x25
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"REG_NR52_MASTERCTL", # 0x26
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"REG_UNK", # 0x27
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"REG_UNK", # 0x28
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"REG_UNK", # 0x29
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"REG_UNK", # 0x2A
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"REG_UNK", # 0x2B
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"REG_UNK", # 0x2C
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"REG_UNK", # 0x2D
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"REG_UNK", # 0x2E
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"REG_UNK", # 0x2F
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"REG_WAVE_PATTERN_0", # 0x30
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"REG_WAVE_PATTERN_1", # 0x31
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"REG_WAVE_PATTERN_2", # 0x32
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"REG_WAVE_PATTERN_3", # 0x33
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"REG_WAVE_PATTERN_4", # 0x34
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"REG_WAVE_PATTERN_5", # 0x35
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"REG_WAVE_PATTERN_6", # 0x36
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"REG_WAVE_PATTERN_7", # 0x37
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"REG_WAVE_PATTERN_8", # 0x38
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"REG_WAVE_PATTERN_9", # 0x39
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"REG_WAVE_PATTERN_A", # 0x3A
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"REG_WAVE_PATTERN_B", # 0x3B
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"REG_WAVE_PATTERN_C", # 0x3C
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"REG_WAVE_PATTERN_D", # 0x3D
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"REG_WAVE_PATTERN_E", # 0x3E
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"REG_WAVE_PATTERN_F", # 0x3F
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]
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def chunks(lst, n):
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for i in range(0, len(lst), n):
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yield lst[i:i + n]
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class DB:
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l = []
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def __init__(self):
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self.l = []
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def __str__(self):
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out = []
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for chunk in chunks(self.l, 8):
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out.append(f" db {', '.join(chunk)}")
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return "\n".join(out) + "\n"
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def __repr__(self):
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return str(self)
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def __len__(self):
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return len(self.l)
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def add(self, *args):
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if len(args) == 1:
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self.l.append(f"${args[0]:02X}")
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else:
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self.l.append(register_names[args[0]])
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self.l.append(f"${args[1]:02X}")
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def trim(self):
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while self.l[-1] == "$FF":
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self.l.pop()
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for c, v in enumerate(register_names):
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if v != "REG_UNK":
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print(f"DEF {v} EQU ${c:02X}")
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print()
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print("sMusicMenu::")
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with open("menu.vgm", "rb") as f:
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data = f.read()
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header = vgm_header.parse(data)
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data_offset = 0x34 + header.vgm_data_offset
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data = data[data_offset:]
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db = DB()
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ctr = 0
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last = None
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while len(data) > 0:
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if data.startswith(b'\x67\x66'):
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data = data[3:]
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data = data[Int32ul.parse(data) + 4:]
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elif data.startswith(b'\xB3'):
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b3 = b3_command.parse(data)
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if last == 0x62:
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print(db)
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db = DB()
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db.add(b3.reg + 0x10, b3.data)
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last = 0xB3
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data = data[3:]
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elif data.startswith(b'\x62'):
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db.add(0xFF)
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last = 0x62
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data = data[1:]
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elif data.startswith(b'\x66'):
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if len(db) > 0:
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db.trim()
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db.add(0xFE)
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print(db, end="")
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break
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else:
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print(f"Unknown command: ${data[0]:02X}")
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data = data[1:]
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print("sMusicMenuEnd::")
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2053
src/sfx.asm
2053
src/sfx.asm
File diff suppressed because it is too large
Load Diff
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@ -121,6 +121,9 @@ SwitchToGameplay::
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ld a, LCDCF_ON | LCDCF_BGON | LCDCF_OBJON | LCDCF_BLK01
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ld a, LCDCF_ON | LCDCF_BGON | LCDCF_OBJON | LCDCF_BLK01
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ldh [rLCDC], a
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ldh [rLCDC], a
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; Music end
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call SFXKill
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; Make sure the first game loop starts just like all the future ones.
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; Make sure the first game loop starts just like all the future ones.
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wait_vblank
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wait_vblank
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wait_vblank_end
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wait_vblank_end
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@ -123,6 +123,11 @@ SwitchToTitle::
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ld a, LCDCF_ON | LCDCF_BGON | LCDCF_BLK01
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ld a, LCDCF_ON | LCDCF_BGON | LCDCF_BLK01
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ldh [rLCDC], a
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ldh [rLCDC], a
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; Music start
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call SFXKill
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ld a, MUSIC_MENU
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call SFXEnqueue
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; Make sure the first game loop starts just like all the future ones.
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; Make sure the first game loop starts just like all the future ones.
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wait_vblank
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wait_vblank
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wait_vblank_end
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wait_vblank_end
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@ -178,12 +183,24 @@ TitleEventLoopHandler::
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.left
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.left
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ldh a, [hLeftState]
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ldh a, [hLeftState]
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cp a, 1
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cp a, 1
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jp z, DecrementOption
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cp a, 16
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jr c, .right
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ldh a, [hFrameCtr]
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and 3
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cp a, 3
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jr nz, .right
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jr nz, .right
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jp DecrementOption
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jp DecrementOption
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.right
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.right
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ldh a, [hRightState]
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ldh a, [hRightState]
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cp a, 1
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cp a, 1
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jp z, IncrementOption
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cp a, 16
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jr c, .done
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ldh a, [hFrameCtr]
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and 3
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cp a, 3
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jr nz, .done
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jr nz, .done
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jp IncrementOption
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jp IncrementOption
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Loading…
Reference in New Issue